1. Field of the Invention
The invention relates to non-volatile electronic memories that can be written and erased electrically. It also relates to the method of their management. These memories, known as EEPROMs, are essentially memories whose memory cells each include at least one MOS technology floating-gate transistor. The aim of the invention is to create an EEPROM type memory structure that is more compact than presently available structures, through the elimination of a selection transistor used in the standard EEPROM type memory cell. Consequently, it becomes possible, with the invention, to obtain a gain of about 50% in surface area. This then makes it possible to obtain memory arrays whose density is close to that of FLASH type structures while maintaining the advantages of EEPROM type structures over FLASH type structures.
2. Discussion of the Related Art
It may be recalled that floating-gate EPROMs are memories that are electrically programmable and non-erasable (or erasable by ultraviolet rays which is not the same thing as being electrically erasable). The electrical phenomenon of the programming of these EPROM memories is a phenomenon of thermal agitation in the conduction channel under the effect of a current saturation. This phenomenon is not reversible. The memories known as EEPROMs are electrically erasable and programmable. The phenomenon of programming and erasure, which is reversible, is a tunnel effect phenomenon. As opposed to the current saturation phenomenon, also called hot carrier phenomenon, the tunnel phenomenon has the advantage of not consuming current. The high programming and erasure voltages may then be produced by circuits internal to the memory (load pumps and multipliers). The so-called FLASH memories are hybrid memories. That is, they are programmable by hot carriers and erased by tunnel effect. In practice, the voltages applied to the gates, drains and sources of the floating-gate transistors of the memory cells provide information on the type of programming and erasure that is brought about.
The advantages of the memory cells of the invention over FLASH cells are essentially as follows.
First, the memory cells of the invention have greater endurance, for the erasure and writing operations use only the tunnel effect while the FLASH memories use, in turn, the tunnel effect and the currents of hot electrons.
Second, the memory cells of the invention operation at low supply voltage, for the tunnel current is far smaller than the current of hot carriers, which greatly simplifies the generation of the high voltages needed for the programming mechanisms within the integrated circuit itself. This makes them usable especially in portable applications, powered by cells or batteries, at voltages of the order of 2 or 3 volts.
FIG. 1 enables a description of the structure of an EEPROM type memory array of the related art.
The memory array shown is addressed in matrix form by means of row selection lines SR, SR+1 called word lines and lines SC for the supply of control gates of the floating-gate transistors of the cells of a column. In a column, the cells are assembled in a word of 8, 16, 32, . . . bits as the case may be. FIG. 1 shows one column with an index c and rows of indices r and r+1 in this column. FIG. 1 shows two bytes, eight bit lines BLc to BLc+7 being attached to the column c. It can be seen that the two bytes are shown symmetrically with respect to a switched horizontal ground line called GNDH. The line GNDH is connected to the ground GND of the circuit by connection to a ground line V series-connected with a switching transistor MC whose gate is referenced SW. With each column, therefore, there are associated eight bit lines, one line SC and one ground connection line V. The read circuits are connected to the bit lines of the cells of a word at the time of reading.
An elementary cell, surrounded in FIG. 1, is formed by a selection transistor Msel and a floating-gate transistor Mlec for storage and reading. The transistor Msel enables the conditional connection of a bit line, BLc+7 in this case, to the drain of the transistor Mlec. The transistor Mlec has two stacked gates, one lower floating gate FG and one upper control gate CG. These two gates are separated from each other by a gate oxide that is similar or has a thickness different from the one between the gate FG and the channel of the transistor Msel. The control gates CG of the transistors of one and the same byte are all connected together and connected to the line SC by a control gate selection transistor MCG.
The transistor Mlec has a tunnel window tu with a thickness of about 80 nm, interposed between its floating gate and its drain. In one example, for an EEPROM cell, the thickness of this tunnel window is 80 nm while it is 120 nm for a FLASH EPROM cell. The gate oxide is 200 nm for an EPROM cell. The window tu has the role of letting through a tunnel current (which is very small) between the drain and the floating gate of the transistor Mlec as soon as the voltage between the faces of the tunnel oxide goes beyond a critical threshold of about 10 volts, in fact as soon as the electrical field goes beyond 15.106 V/m. Depending on whether this voltage is positive or negative, the floating gate will be charged negatively or positively. It can therefore be seen that there is a permanent potential difference at the terminals of a capacitor formed by the stack of the gates CG and FG.
The threshold voltage Vt of a MOS transistor is the voltage between the control gate and the source of this transistor, starting from which the transistor becomes conductive. If Vt is the intrinsic threshold voltage of the transistor Msel, the conduction of this transistor Msel is related to the difference V(FG)-Vt where V(FG) is a floating-gate voltage due to the accumulation of the electrical charges at this floating gate. By furthermore applying a read voltage to the gate CG, this difference V(FG)-Vt enables or does not enable the transistor Msel to become conductive. The result thereof is that the conduction of the transistor Mlec depends on the charge of the capacitor CG/FG.
When the transistors MC and Msel are on, the current between a bit line BLi and the ground line V depends on the state of programming of the cell. By applying an appropriate read voltage CGref to the gates CG and by comparing a current flowing between each bit line BL and the line V with a reference value, it is possible to make a remote detection of the state of charging of the floating gate. The result of the comparison is converted into a binary information element.
Typically, it is said that if the current is smaller than the reference current, the cell is erased and corresponds to the storage of a binary 0 value. In a P substrate device using CMOS technology, the erased cells correspond to transistors with electrons stored at the floating gate. If not, the cell is said to be programmed and corresponds to the storage of a binary 1 value (with holes on the floating gate). In read mode, the bit lines of the bytes of the different columns are multiplexed and connected to read amplifiers which are broadly speaking current comparators. This part shall not be described in further detail. It is the same in the invention as in the related art.
The conditions of polarization of the different control nodes of the cells of FIG. 1 are summarized in FIG. 2. In FIG. 2, the nodes SW, SC, BL, SR and SR', which is different from SR are those referred to up till now. The operations are the standard ones of memory management. The spaces in the table show the voltages to be applied to the nodes to obtain the performance of the operation. The write operations may comprise erasure operations only, possibly programming operations only or erasure operations followed by programming operations. The voltage Vcc is equal to about 5 volts and the voltage VPP is equal to about 12 volts.
The programming of a word is done conventionally in two phases:
a phase for the erasure of all the cells of this word--charges are injected (negative charges for a P type substrate) into all the floating gates of the word; PA1 a selective programming phase (the removal of the negative charges and injection of the positive charges for a P type substrate) for the programming of the cells that have to be programmed. PA1 if the cell does not form part of the same row (r) as the cell to be programmed, the selection transistors Msel and MCG are off: they are taken to 0 in both cases. If the cell does not form part of the same column as the cell to be programmed, the rows V and BLi are disconnected from the high voltage (by a multiplexer circuit that is not described here). PA1 *for a first cell to be selected, PA1 in erasure: a source connection of the floating-gate transistor of this first cell, called the first transistor, is subjected to a ground voltage (0V) of the integrated circuit, a drain connection of this first transistor is subjected to a ground voltage and a control gate of this first transistor is subjected to a high programming voltage which, with respect to the ground voltage, is greater than a supply voltage of an integrated circuit, PA1 in programming: the source connection of this first transistor is placed in a state of high impedance, the drain connection of this first transistor is subjected to the high programming voltage or to a high impedance depending on the nature of a bit to be written and the control gate of this first transistor is subjected to a ground voltage, PA1 in reading: the source connection of this first transistor is subjected to the ground voltage, the drain of this first transistor is connected to a threshold read amplifier and the control gate of this first transistor is connected to a first intermediate read control voltage between the ground voltage and the supply voltage; PA1 *for a second cell that is not to be selected, PA1 a) the cell is erased, then PA1 b) it is programmed with a partial programming effect by withdrawing electrical charges from the floating gate of the transistor, and then the contents of the cell are read; PA1 c) the steps from b) are started again in increasing the programming effect until the programming level is deemed to be sufficient.
It will be assumed that this process is also applied in the context of the invention and its variants.
The programming operation is the most critical one. The switched ground line V is floating during programming (SW taken to 0) to prevent a direct passage of current between the bit lines BLi taken to VPP and the ground GND, when the floating gate FD gets charged positively. Indeed, in this case, the transistor Mlec could become conductive as soon as its floating gate becomes positive. Owing to the architecture adopted, it can be seen that neither the control gate nor the source of the transistor Msel (having a common node with the drain of the transistor Mlec) of a cell of a byte not selected for the programming or erasure are subjected to high voltage:
The result thereof is that the programming of the cell has no effect on the other cells of the memory array which are not to be programmed.
An alternative embodiment can be used to reduce the surface area of the memory array by combining the cells not into n bytes in one and the same row but into a single word of 8.times.n cells for the entire row. The term used in this case is &lt;&lt;page&gt;&gt;. The advantage of this variant lies in the gain and space due to the elimination of (n-1) lines SC associated with their selection transistors MCG. The gain in terms of space requirement may go up to 20%. The drawback of this is the loss of the individual programming at the level of the byte. The programming thereafter is done only page by page. This type of structure lends itself well to large-sized memories wherein the data elements are renewed by blocks. This variant is schematically similar to that of FIG. 1 except that there is no longer one control gate selection transistor MCG every eight cells but one such transistor for a full page (or for a smaller proportion but for more than eight cells). This variant is conventionally called PEROM (P for page), the standard structure being called EEPROM.